The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2026
Filed:
Sep. 22, 2022
International Business Machines Corporation, Armonk, NY (US);
Benjamin Neil Trombley, Hopewell Junction, NY (US);
Chung-Lung K. Shum, Wappingers Falls, NY (US);
Paul G. Villarrubia, Austin, TX (US);
K. Paul Muller, Wappingers Falls, NY (US);
Michael Hemsley Wood, Wilmington, DE (US);
Daniel Arthur Gay, Lagrangeville, NY (US);
Hua Xiang, San Jose, CA (US);
Karl Evan Smock Anderson, Poughkeepsie, NY (US);
Erica Stuecheli, Austin, TX (US);
Michael Alexander Bowen, Poughkeepsie, NY (US);
Randall J. Darden, Ridgedale, MO (US);
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Abstract
A method, system, and computer program product for bit flip aware latch placement in integrated circuit generation are provided. The method identifies a chip design for an integrated circuit. A set of chip design constraints, associated with the chip design, is identified. A set of checking groups, associated with a plurality of latches to be placed in the chip design, is determined. Based on the set of chip design constraints and the set of checking groups, a placement scheme for the plurality of latches is selected. The method places the plurality of latches within the chip design based on the placement scheme and the set of checking groups.