The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2026
Filed:
Nov. 22, 2022
Applicant:
D2s, Inc., San Jose, CA (US);
Inventors:
Donald Oriordan, Sunnyvale, CA (US);
Akira Fujimura, Saratoga, CA (US);
George Janac, Saratoga, CA (US);
Assignee:
D2S, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/31 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/08 (2023.01);
U.S. Cl.
CPC ...
G06F 30/31 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/08 (2013.01);
Abstract
A method for manufacturing-aware editing of circuit layouts driven by predictions regarding predicted manufactured wafer contours generated by a machine-trained network. The method allows for fast edit loops in interactive editing timeframes, in which the predicted manufactured wafer contours corresponding to design edits are presented within seconds of the edits themselves. In some embodiments, the wafer contours take mask OPC/ILT and lithography effects into account, as determined by the machine trained network.