The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Oct. 19, 2022
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Ankur Bal, Greater Noida, IN;

Sri Ram Gupta, Noida, IN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 29/26 (2006.01); H03K 3/03 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
G01R 29/26 (2013.01); H03K 3/0315 (2013.01); H03K 3/037 (2013.01);
Abstract

A measurement is made of jitter present in a jittery clock signal. A digital sinusoid generator circuit clocked by the jittery clock signal generates a pulse density modulation (PDM) signal corresponding to a sinusoid waveform. The PDM signal is converted by a sigma-delta modulator circuit to an oscillating frequency signal with an output of digital values digital values indicative of oscillating frequency signal phase. Responsive to the jittery clock signal, the digital values indicative of oscillating frequency signal phase are sampled. A digital differentiator circuit determines a digital difference between consecutive samples of the digital values indicative of oscillating frequency signal phase. The digital difference is processed by a digital signal processing circuit to generate a frequency spectrum and determine from signal-to-noise ratio a measurement of jitter in the jittery clock signal.


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