The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Apr. 29, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Satish Damaraju, El Dorado Hills, CA (US);

Scott E. Siers, Elk Grove, CA (US);

Altug Kokar, El Dorado Hills, CA (US);

Wilfred Gomes, Portland, OR (US);

Mark C. Davis, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2023.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/167 (2013.01); H01L 23/5386 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 24/16 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01);
Abstract

Embodiments of a microelectronic assembly comprise a first integrated circuit (IC) die including a plurality of first circuits separated by scribe regions, and a plurality of second IC dies coupled to the first IC die, each one of the second IC dies being coupled proximate and adjacent to a corresponding one of the first circuits and conductively coupled to the corresponding one of the first circuits. One or more of the second IC dies comprises a second circuit different from the first circuit, adjacent ones of the first circuits are coupled by a conductive pathway through the corresponding scribe regions, and the first IC die and the second IC die are coupled by interconnects having a pitch not more than 10 micrometers between adjacent interconnects.


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