The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Dec. 13, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Kisik Choi, Watervliet, NY (US);

Nicolas Jean Loubet, Guilderland, NY (US);

Theodorus E. Standaert, Clifton Park, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/28141 (2013.01); H01L 23/5286 (2013.01); H01L 23/535 (2013.01); H10D 30/024 (2025.01); H10D 30/6728 (2025.01); H10D 62/121 (2025.01); H10D 64/018 (2025.01); H10D 84/0149 (2025.01); H10D 84/017 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H10D 88/101 (2025.01);
Abstract

A semiconductor device is provided. The semiconductor device includes source/drain (S/D) epitaxy, a gate stack adjacent to the S/D epitaxy, a semiconductor layer underlying the gate stack and including a semiconductor material surrounded by an inner spacer, an etch stop layer underlying the semiconductor layer, back trench S/D epitaxy and a self-aligned backside contact. The backside trench S/D epitaxy contacts the S/D epitaxy and is insulated from the semiconductor material by the inner spacer. The self-aligned backside contact contacts the backside trench S/D epitaxy and is insulated from the semiconductor material by the etch stop layer.


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