Circuit and method for channel randomization based on time-interleaved adc

Abstract

A circuit for channel randomization based on time-interleaved ADC includes: a channel selection module for outputting M clock reception control signals and encoded N data reception control signals based on a main clock and a generated random number; a multi-phase clock distribution module for generating N multi-phase clocks according to a sampling main clock, redistributing the multi-phase clocks according to the clock reception control signals, and outputting M redistributed clock signals; a time-interleaved ADC module for outputting M output data and a corresponding number of channel quantization completion signals according to the redistributed clock signals; an adjustable delay module for setting a delay length for the data reception control signals; and a timing distribution control module for controlling, according to delayed data reception control signals and the channel quantization completion signals, the output data to be output sequentially in chronological order.