The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

May. 08, 2023
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Siva Kumar Chinthu, Bangalore, IN;

Venu Gopal Reddy Ara, Bangalore, IN;

Devesh Dwivedi, Bangalore, IN;

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); H03K 19/0175 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01); H03K 19/017509 (2013.01); H03K 19/20 (2013.01);
Abstract

Embodiments of the disclosure provide a customizable logic cells and related methods to form the same. A structure of the disclosure includes a first pair of complementary transistors connected in series between a first voltage node and a second voltage node. Each transistor of the first pair includes a gate coupled to a first input node. A second pair of complementary transistors is connected in series between the first voltage node and the second voltage node in an opposite orientation from the first pair of complementary transistors. Each transistor of the second pair includes a gate coupled to a second input node. An output line is coupled to a first electrical connection between the first pair complementary transistors and a second electrical connection between the second pair of complementary transistors.


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