Memory device with error correction code

Abstract

A memory device including a memory array, an ECC circuit, and a memory controller is provided. The memory array is configured to store a memory word. The memory word includes a data, at least one parity bit and a flag. The ECC circuit is configured to generate the at least one parity bit of the data, and detect and correct an error of the data read out from the memory array based on the at least one parity bit of the read data. The memory controller is coupled to the memory array. The memory controller is configured to perform a read operation to read the memory word from the memory array, and perform a program operation to program the memory word into the memory array. The memory controller is configured to determine whether the ECC circuit is enabled during the read operation or the program operation to be performed on the memory word according to the memory word. The memory word is configured to indicate a predetermined state selected from at least two states of the ECC circuit.