Memory device, operation method thereof, memory system, and memory controller

Abstract

According to one aspect of the present disclosure, a memory device is provided. The memory device may include a memory cell array including a plurality of memory cells. A preset number of the memory cells may form a code word. The memory device may include a peripheral circuit coupled with the memory cell array. The peripheral circuit may be configured to obtain M first results corresponding to at least one code word at M target read voltages. The peripheral circuit may be configured to obtain a predicted valley voltage according to the M first results and the M target read voltages in conjunction with a preset function model. The peripheral circuit may be configured to determine a target valley voltage based on the predicted valley voltage. The target valley voltage may be configured as a read voltage for a read operation on the at least one code word.