The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2026

Filed:

Jun. 14, 2023
Applicant:

Tong Hsing Electronic Industries, Ltd., Taipei, TW;

Inventors:

Chung-Hsiao Lien, Taipei, TW;

Wei-Ming Lu, Taipei, TW;

Jia-Yi Wu, Taipei, TW;

Zzu-Chi Chiu, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 24/04 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 23/49838 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05541 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/05578 (2013.01); H01L 2224/05583 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/48095 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49111 (2013.01); H01L 2224/49175 (2013.01);
Abstract

A power chip packaging structure includes: a ceramic substrate; a first and a second top metal layers are formed on the ceramic substrate; a bottom metal layer formed on the ceramic substrate; a power chip having an active surface and a chip back surface. The active surface has a contact pad, and the chip back surface is connected to the first top metal layer. One or more first copper layers are formed on the contact pad, a top surface of the first copper layer has a peripheral region and an arrangement region surrounded by the peripheral region. Multiple second copper layers are formed in the arrangement region and separated from each other. Each of multiple wires is respectively connected to the second copper layer with one end and connected to the second top metal layer with the other end.


Find Patent Forward Citations

Lien, Chung-Hsiao. (2026). Power chip packaging structure (U.S. Patent No. 12538832). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12538832

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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