The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2026

Filed:

Jun. 21, 2022
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Da-Jun Lin, Kaohsiung, TW;

Fu-Yu Tsai, Tainan, TW;

Bin-Siang Tsai, Changhua County, TW;

Chung-Yi Chiu, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/85 (2025.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/824 (2025.01);
U.S. Cl.
CPC ...
H10D 62/8503 (2025.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/824 (2025.01);
Abstract

A semiconductor device includes a III-V compound semiconductor layer, a silicon-doped III-V compound barrier layer, and a silicon-rich tensile stress layer. The silicon-doped III-V compound barrier layer is disposed on the III-V compound semiconductor layer, and the silicon-rich tensile stress layer is disposed on the silicon-doped III-V compound barrier layer. A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A silicon-rich tensile stress layer is formed on the III-V compound barrier layer. An annealing process is performed after the silicon-rich tensile stress layer is formed. A part of silicon in the silicon-rich tensile stress layer diffuses into the III-V compound barrier layer for forming a silicon-doped III-V compound barrier layer by the annealing process.


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