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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12538479 B1

PDFFull Text
Date of Patent:
Jan. 27, 2026

Filed:

Aug. 08, 2023

Memory devices and methods for forming the same

Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Yanhong Wang, Wuhan, CN;

Wei Liu, Wuhan, CN;

Yaqin Liu, Wuhan, CN;

Shiqi Huang, Wuhan, CN;

Liang Chen, Wuhan, CN;

Assignee:

YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan, CN;

Attorney:

BAYES PLLC

Primary Examiner:

Brook Kebede

Int. Cl.
CPC ...
H10B 12/00 (2023.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); H10B 63/10 (2023.01);
U.S. Cl.
CPC ...
H10B 12/50 (2023.02); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); H10B 12/03 (2023.02); H10B 12/05 (2023.02); H10B 12/09 (2023.02); H10B 12/315 (2023.02); H10B 12/485 (2023.02); H10B 63/10 (2023.02);
Abstract

A memory device includes a memory array structure, a first peripheral circuit, and a second peripheral circuit. The memory array structure includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The first peripheral circuit is disposed at one side of the memory array structure and includes a first side in contact with the memory array structure and a second side opposite to the first side in a first direction. The second peripheral circuit is disposed in contact with the second side of the first peripheral circuit away from the memory array structure.

Find Patent Forward Citations

Wang, Yanhong. (2026). Memory devices and methods for forming the same (U.S. Patent No. 12538479). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12538479

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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