Configurable delay chain

Abstract

An integrated circuit includes a configurable delay chain, which contains a chain of binary delay blocks. Each binary delay block includes the following. Inputs receive an input signal, a select signal and a test control signal. A delay branch transmits the input signal with a delay, and a bypass branch transmits the input signal without the delay. Selector circuitry is connected to the delay branch and to the bypass branch. The selector circuitry selects either the delay branch or the bypass branch according to the select signal. According to the test control signal, test circuitry produces a test signal to test the selector circuitry.