The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2026
Filed:
May. 16, 2024
Applicant:
Stmicroelectronics International N.v., Geneva, CH;
Inventor:
Rohit Kumar Gupta, Noida, IN;
Assignee:
STMicroelectronics International N.V., Geneva, CH;
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/012 (2006.01); H03K 3/037 (2006.01); H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0375 (2013.01); H03K 3/012 (2013.01); H03K 3/356008 (2013.01);
Abstract
A retention flip flop includes a first latch, a second latch, and a retention latch. The first and second latches are powered by an interruptible primary supply voltage while the retention latch is powered by a secondary supply voltage that is not interrupted. The retention flip-flop receives a single retention control signal that controls whether the flip-flop is in a standard mode or a retention mode. In the retention mode, the flip-flop clock signal is paused.
Gupta, Rohit. (2026). Single pin clock-free retention flip-flop (U.S. Patent No. 12537516). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12537516
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile