The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2026

Filed:

Nov. 06, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Andre Xian Ming Chang, Seattle, WA (US);

Aliasger Tayeb Zaidy, Seattle, WA (US);

Eugenio Culurciello, West Lafayette, IN (US);

Jaime Cummins, Bainbridge Island, WA (US);

Marko Vitez, Trieste, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/00 (2019.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01); G06F 7/544 (2006.01); G06F 9/50 (2006.01); G06F 17/16 (2006.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01);
U.S. Cl.
CPC ...
G06N 3/08 (2013.01); G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 7/5443 (2013.01); G06F 9/5027 (2013.01); G06F 17/16 (2013.01); G06N 3/063 (2013.01);
Abstract

Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM). A compiler can convert a description of an artificial neural network into a generic result of compilation according to a specification of a generic Deep Learning Accelerator and then map the first result of compilation into a platform-specific result according to a specification of a specific hardware platform of Deep Learning Accelerators. The platform-specific result can be stored into the RAM of the integrated circuit device to enable the integrated circuit device to autonomously perform the computation of the artificial neural network in generating an output in response to an input to the artificial neural network.


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