Soc architecture with secure, selective peripheral enabling/disabling

Abstract

A SOC includes a core, peripherals, and a bus for interconnecting the core and peripherals. Some peripherals can be selectively enabled or disabled on-demand. The SoC further includes peripheral enabling/disabling electronics and peripheral enabling/disabling circuitry coupled to the peripherals. The peripheral enabling/disabling electronics are directly connected to the peripheral enabling/disabling circuitry and are configured to store information items related to an enabled/disabled peripheral configuration, indicate the peripherals that are enabled and the peripherals that are disabled according to the enabled/disabled peripheral configuration, and provide the peripheral enabling/disabling circuitry with signals based on the stored information items. The peripheral enabling/disabling circuitry allows operation of the enabled peripherals and prevents operation of the disabled peripherals based on the signals received from the peripheral enabling/disabling electronics. The peripheral enabling/disabling electronics implement a secure mechanism allowing access to the peripheral enabling/disabling electronics and modification of the stored information items if security criteria are met.