Memory device, operating method of memory device, and memory system including memory device

Abstract

A memory device includes a memory cell array that includes a plurality of memory cells disposed in a plurality of rows, an eraser detector that stores vulnerable row data including a location of an estimation error corresponding to a vulnerable row among the plurality of rows, an error correction code (ECC) engine that decodes first data read from the memory cell array based on the vulnerable row data to generate information on a first error included in the first data in response to a read command and corrects the first error to generate second data, and a flag generator that generates a decoding flag indicating a decoding state of the ECC engine based on the vulnerable row data, the information on the first error, and the second data.