The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2026
Filed:
Jun. 21, 2024
Synopsys, Inc., Sunnyvale, CA (US);
Alexander Rabinovitch, Shrewsbury, MA (US);
Baijayanta Ray, Bengaluru, IN;
Synopsys, Inc., Sunnyvale, CA (US);
Abstract
Preemptive stoppage of design clocks for processing blocking direct programming interface (DPI) calls is described. A blocking DPI call is received at a first field programable gate array (FPGA) of a plurality of FPGAs of an emulation system. The DPI call is received at a system clock cycle, K, of a system clock of the emulation system. Prior to the first FPGA calling the blocking DPI call, an amount of delay, N, associated with the blocking task is determined. The emulation system performs operations to communicate a stop clock instruction to each of a set of FPGAs of the plurality of FPGAs such that design clocks of each of the set of FPGAs are stopped in unison at a system clock cycle of K+N. The emulation system calls the blocking task at a system clock cycle of K+N+1.