The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Jun. 16, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Tsung-Chieh Hsiao, Changhua County, TW;

Chung-Yun Wan, Changhua County, TW;

Liang-Wei Wang, Hsinchu, TW;

Dian-Hau Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/50 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); H10B 80/00 (2023.01); H10D 1/68 (2025.01);
U.S. Cl.
CPC ...
H01L 23/50 (2013.01); H01L 24/02 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/09 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 80/00 (2023.02); H10D 1/692 (2025.01); H01L 2224/0231 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/09103 (2013.01); H01L 2224/09181 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1437 (2013.01);
Abstract

One aspect of the present disclosure pertains to a method. The method includes receiving a first circuit structure having semiconductor devices, an interconnect structure, first feedthrough vias, top metal lines, redistribution vias, and bond pads. The method includes dicing the first circuit structure to form a top die having a top semiconductor device. The method includes forming a stacked integrated circuit (IC) structure by bonding the top die to a second circuit structure, the second circuit structure having second semiconductor devices, a second interconnect structure, second redistribution vias, and second bond pads. The method includes forming IC top metal lines over the first feedthrough vias, forming an IC passivation layer over the IC top metal lines, forming metal-insulator-metal (MIM) capacitor structures in the IC passivation layer, and forming IC redistribution vias penetrating through the MIM capacitor structures and the IC passivation layer to land on the IC top metal lines.


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