The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

May. 12, 2022
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Kushal Kshirsagar, Warwick, RI (US);

Eung San Cho, Torrance, CA (US);

Arun Kumar Gnanappa, Regensburg, DE;

Wenkang Huang, East Greenwich, RI (US);

Angela Kessler, Sinzing, DE;

Marcel Rene Mueller, Bendorf, DE;

Stephen Pullen, Olympia, WA (US);

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3675 (2013.01); H01L 21/4853 (2013.01); H01L 21/4871 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19105 (2013.01);
Abstract

A semiconductor assembly includes a device carrier that includes a dielectric core region and a plurality of contact pads disposed on an upper surface, a semiconductor device package having a plurality of lower surface terminals, a discrete passive element comprising a main body and a pair of leads, and a region of gap filler material, wherein the semiconductor device package is mounted on the device carrier with the lower surface terminals facing and electrically connected to a group of the contact pads, wherein the discrete passive element is mounted on the device carrier with the pair of leads electrically connecting with contact surfaces on the device carrier, and wherein the region of gap filler material is arranged between a lower surface of the main body and the upper surface of the semiconductor device package and thermally couples the semiconductor device package to the discrete passive element.


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