The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Oct. 14, 2021
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Venugopal Pabba, Ranga Reddy, IN;

Biral Rasikbhai Patel, Ahmedabad, IN;

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 89/10 (2025.01); G06F 30/343 (2020.01); G06F 30/3953 (2020.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 89/10 (2025.01); G06F 30/343 (2020.01); G06F 30/3953 (2020.01); H10D 84/0191 (2025.01); H10D 84/038 (2025.01);
Abstract

An N-well cell stored as a digital representation with a non-transitory computer readable medium. The N-well cell is used within a circuit block of an integrated circuit device. The N-well cell includes a first N-well electrically connected to a first power rail providing a first supply voltage. The first N-well further includes a second N-well electrically connected to the first power rail, and a third N-well electrically connected to a second power rail providing a second supply voltage different from the first supply voltage. The third N-well is positioned between the first N-well and the second N-well. The third N-well includes a first logic sub-block electrically connected to the second power rail, and a second logic sub-block electrically connected to the second power rail.


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