The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Nov. 17, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hsiao-Chun Chang, Hsinchu, TW;

Guan-Jie Shen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/3213 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01);
U.S. Cl.
CPC ...
H10D 64/017 (2025.01); H01L 21/0259 (2013.01); H01L 21/28088 (2013.01); H01L 21/32137 (2013.01); H01L 21/32139 (2013.01); H10D 30/024 (2025.01); H10D 30/031 (2025.01); H10D 30/6211 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 62/151 (2025.01); H10D 64/018 (2025.01);
Abstract

The present disclosure describes a semiconductor device with modulated gate structures and a method for forming the same. The method includes forming a fin structure, depositing a polysilicon layer over the fin structure, and forming a photoresist mask layer on the polysilicon layer. The method further includes etching, with a first etching condition, the polysilicon layer not covered by the photoresist mask layer and above a top surface of the fin structure. The method further includes etching, with a second etching condition, the polysilicon layer not covered by the photoresist mask layer and below the top surface of the fin structure, where the etched polysilicon layer below the top surface of the fin structure is narrower than the etched polysilicon layer above the top surface of the fin structure. The method further includes removing the etched polysilicon layer to form a space and forming a gate structure in the space.


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