The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Dec. 07, 2022
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventor:

Masanori Tsutsumi, Yokkaichi, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/27 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 41/27 (2023.02); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02);
Abstract

A bonded assembly includes first memory die bonded to a logic die. The first memory die includes a first alternating stack of first insulating layers and first electrically conductive layers, first memory openings vertically extending through the first alternating stack, first memory opening fill structures located within the first memory openings and containing a respective vertical stack of first memory elements and a respective vertical semiconductor channel, electrically conductive first side-contact via structures vertically extending through each layer within the first alternating stack and contacting a sidewall of a respective one of the first electrically conductive layers, and first memory-side bonding pads. The logic die includes a peripheral circuitry configured to control operation of the first memory die, logic-side metal interconnect structures, and logic-side bonding pads that are bonded to the first memory-side bonding pads.


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