The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2026
Filed:
Apr. 19, 2019
Applicant:
Lam Research Corporation, Fremont, CA (US);
Inventors:
Anand Chandrashekar, Fremont, CA (US);
Eric H. Lenz, Livermore, CA (US);
Leonard Wai Fung Kho, San Francisco, CA (US);
Jeffrey Charles Clevenger, Fremont, CA (US);
In Su Ha, Fremont, CA (US);
Assignee:
Lam Research Corporation, Fremont, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01J 37/32 (2006.01); H01L 21/02 (2006.01); H01L 21/687 (2006.01);
U.S. Cl.
CPC ...
H01J 37/32449 (2013.01); H01J 37/32642 (2013.01); H01J 37/32715 (2013.01); H01L 21/02175 (2013.01); H01L 21/02186 (2013.01); H01L 21/68721 (2013.01); H01L 21/68735 (2013.01); H01J 2237/332 (2013.01);
Abstract
Provided herein are methods and apparatuses for controlling uniformity of processing at an edge region of a semiconductor wafer. In some embodiments, the methods include exposing an edge region to treatment gases such as etch gases and/or inhibition gases. Also provided herein are exclusion ring assemblies including multiple rings that may be implemented to provide control of the processing environment at the edge of the wafer.