The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Aug. 31, 2023
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

National Taiwan University, Taipei, TW;

Inventors:

Hsin-Cheng Lin, Taipei, TW;

Tao Chou, New Taipei, TW;

Kuan-Ying Chiu, Taoyuan, TW;

Chee-Wee Liu, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); H01L 23/48 (2006.01); H10B 10/00 (2023.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); H01L 23/481 (2013.01); H10B 10/12 (2023.02); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 64/017 (2025.01);
Abstract

An SRAM cell includes a first active region, a first gate structure, a second gate structure, and a first source/drain contact region. The first gate structure is over the first active region and forms a pull-up transistor with the first active region. The second gate structure is over the first active region and forms a write-assist transistor with the first active region. The write-assist transistor and the pull-up transistor are of a same conductivity type. The first source/drain contact region is over a source/drain of the write-assist transistor and a source/drain of the pull-up transistor.


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