Memory device, operation method, and memory system

Abstract

Examples of the present application disclose a memory device, an operation method, and a memory system. The memory device includes: a bias generation circuit configured to generate a target bias signal according to a data transfer rate of the memory device, wherein the target bias signal varies with a preset data transfer rate range; and a clock buffer circuit coupled with the bias generation circuit and configured to perform, based on the target bias signal, conversion processing on an input clock signal matched with the data transfer rate to obtain a target clock signal used by the memory device.