The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2026
Filed:
Nov. 03, 2023
Micron Technology, Inc., Boise, ID (US);
Akira Goda, Setagaya, JP;
Niccolo′ Righetti, Boise, ID (US);
Shyam Sunder Raghunathan, Woodlands, SG;
Leo Raimondo, Avezzano, IT;
Kishore K. Muccherla, San Jose, CA (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
An apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. A controller is configured to monitor a cumulative amount of read disturb stress experienced by a first erase block by: maintaining a read disturb count corresponding to the first erase block; incrementing the read disturb count by a first amount responsive to read commands issued to addresses corresponding to the first erase block; incrementing the read disturb count by a read disturb scaling factor responsive to read commands issued to addresses corresponding to the second erase block; and incrementing the read disturb count by a program scaling factor responsive to program commands issued to addresses corresponding to the second erase block. The controller can perform an action on the first erase block responsive to the read disturb count exceeding a threshold value.