The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2026
Filed:
Feb. 12, 2024
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 23/535 (2006.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 62/822 (2025.01); H10D 62/832 (2025.01);
U.S. Cl.
CPC ...
H10D 84/013 (2025.01); H01L 23/535 (2013.01); H10D 30/0243 (2025.01); H10D 62/116 (2025.01); H10D 62/151 (2025.01); H10D 62/292 (2025.01); H10D 64/017 (2025.01); H10D 84/0128 (2025.01); H10D 84/0149 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H10D 62/822 (2025.01); H10D 62/832 (2025.01);
Abstract
The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.