The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2026
Filed:
Jul. 10, 2024
Nxp Usa, Inc., Austin, TX (US);
Prakhar Tandon, Hyderabad, IN;
Dileep Ramanolla, Hyderabad, IN;
Uma Maheswara Reddy Poreddy, Hyderabad, IN;
Shivesh Kumar Dubey, Hyderabad, IN;
NXP USA, Inc., Austin, TX (US);
Abstract
A delay locked loop (DLL) circuit includes a voltage-controlled delay line (VCDL) that applies a time delay to a clock-in signal to provide a first output signal and a last output signal. The magnitude of the time delay is based on the control-voltage signal and a delay code. The DLL circuit includes a feedback circuit configured to provide a feedback voltage signal based on the phase difference between the first output signal and the last output signal. In a calibration mode: a fixed voltage source provides a fixed voltage signal as the control-voltage signal for the VCDL; and a delay code setter applies a delay code setting signal to the VCDL to identify a selected-delay-code as the code. In an active mode: the feedback circuit provides the feedback voltage signal as the control-voltage signal for the VCDL; and the VCDL uses the selected-delay-code as the delay code.