The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Dec. 29, 2022
Applicant:

Mediatek Inc., Hsinchu, TW;

Inventors:

Li-Huan Chu, Hsinchu, TW;

Kai-Che Cheng, Hsinchu, TW;

Ming-Tsung Lin, Hsinchu, TW;

Sheng-Feng Liu, Hsinchu, TW;

Chi-Ko Yu, Hsinchu, TW;

Assignee:

MEDIATEK INC., Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/367 (2006.01); H01L 23/495 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H10B 80/00 (2023.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/367 (2013.01); H01L 23/49503 (2013.01); H01L 23/5389 (2013.01); H10B 80/00 (2023.02); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 2224/16113 (2013.01); H01L 2224/48195 (2013.01); H01L 2924/30105 (2013.01);
Abstract

A semiconductor package assembly and an electronic device are provided. The semiconductor package assembly includes a base, a system-on-chip (SOC) package, a memory package and a silicon capacitor die. The base has a first surface and a second surface opposite the first surface. The SOC package is disposed on the first surface of the base and includes a SOC die having pads and a redistribution layer (RDL) structure. The RDL structure is electrically connected to the SOC die by the pads. The memory package is stacked on the SOC package and includes a memory package substrate and a memory die. The memory package substrate has a top surface and a bottom surface. The memory die is electrically connected to the memory package substrate. The silicon capacitor die is disposed on and electrically connected to the second surface of the base.


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