The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Jul. 04, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Liang-Shiuan Peng, Taipei, TW;

Chih-Hung Lu, Hsinchu County, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 21/31105 (2013.01); H01L 21/32131 (2013.01); H01L 21/76801 (2013.01); H01L 21/76838 (2013.01); H01L 2223/54433 (2013.01);
Abstract

The present disclosure provides a method for manufacturing a semiconductor device having a mark. The method includes: providing a substrate including a device region and a peripheral region adjacent to the device region; forming an interconnect layer over the substrate; depositing a first dielectric layer on the interconnect layer; forming a redistribution layer (RDL) over the first dielectric layer in the device region; depositing a second dielectric layer on the RDL in the device region and the first dielectric layer in the device region and the peripheral region; and removing portions of the second dielectric layer, the first dielectric layer and the interconnect structure in the peripheral region to form the mark in the peripheral region.


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