The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Nov. 15, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seunghyun Song, Suwon-si, KR;

Pilkwang Kim, Seoul, KR;

Joohyung You, Seoul, KR;

Sungmin Kim, Incheon, KR;

Yonghee Park, Hwaseong-si, KR;

Young-Seok Song, Hwaseong-si, KR;

Takeshi Okagaki, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10D 30/67 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/151 (2025.01); H10D 64/021 (2025.01);
Abstract

Disclosed are semiconductor devices and fabrication methods thereof. The semiconductor device includes a substrate including first and second regions, a device isolation pattern in the substrate, a lower separation dielectric pattern on the first region of the substrate, first channel patterns on the lower separation dielectric pattern, a first gate electrode on the first channel patterns and including a first gate part between the lower separation dielectric pattern and a lowermost first channel pattern, and first source/drain patterns on opposite sides of the first gate electrode and in contact with lateral surfaces of the first channel patterns. A bottom surface of the lower separation dielectric pattern is at a level higher than or equal to that of a bottom surface of the device isolation pattern. A top end of the lower separation dielectric pattern is at a level higher than that of a bottom surface of the first gate part.


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