The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Mar. 31, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Aslam Haswarey, Portland, OR (US);

Anne Augustine, Chandler, AZ (US);

Yan Fen Shen, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/16 (2006.01); H05K 1/18 (2006.01); H05K 3/00 (2006.01); H05K 3/42 (2006.01);
U.S. Cl.
CPC ...
H05K 1/162 (2013.01); H05K 3/0094 (2013.01); H05K 3/429 (2013.01); H05K 1/181 (2013.01); H05K 2201/09563 (2013.01); H05K 2201/0959 (2013.01); H05K 2201/09636 (2013.01); H05K 2201/09672 (2013.01); H05K 2201/09809 (2013.01); H05K 2201/10378 (2013.01);
Abstract

Embodiments herein relate to systems, apparatuses, or processes to using vias, or plated through holes (PTH), within a substrate or within a sub laminate to create capacitors. The interior of a via may have a first layer, or coating, of an electrically conductive material such as copper, formed on the sides of the via. A second layer including a dielectric material is placed on the first layer of the electrically conductive material. A third layer of electrically conductive material may then be placed on the second layer of the dielectric material. Other embodiments may be described and/or claimed.


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