The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Jun. 20, 2024
Applicant:

Epistar Corporation, Hsinchu, TW;

Inventors:

Min-Hsun Hsieh, Hsinchu, TW;

De-Shan Kuo, Hsinchu, TW;

Chang-Lin Lee, Hsinchu, TW;

Jhih-Yong Yang, Hsinchu, TW;

Assignee:

EPISTAR CORPORATION, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/677 (2006.01); H01L 21/67 (2006.01); H01L 21/683 (2006.01); H10H 20/01 (2025.01);
U.S. Cl.
CPC ...
H01L 21/67721 (2013.01); H01L 21/67144 (2013.01); H01L 21/67288 (2013.01); H01L 21/6773 (2013.01); H01L 21/6836 (2013.01); H10H 20/0137 (2025.01); H01L 2221/68322 (2013.01); H01L 2221/68354 (2013.01); H01L 2221/68368 (2013.01);
Abstract

A chip transferring method includes steps of: providing a plurality of chips on a first load-bearing structure; measuring photoelectric characteristic values of the plurality of chips; categorizing the plurality of chips into a first portion of the plurality of chips and a second portion of the plurality of chips according to the photoelectric characteristic values of the plurality of chips, wherein the second portion of the plurality of chips comprise parts of the plurality of chips which photoelectric characteristic value falls within an unqualified range; removing the second portion of the plurality of chips from the first load-bearing structure; dividing the first portion of the plurality of chips into a plurality of blocks, wherein each of the plurality of blocks comprising multiple chips of the first portion of the plurality of chips; and transferring the first portion of the plurality of chips in one of the plurality of blocks to a second load-bearing structure in single-batch.


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