Built-in self-test circuitry for data in path for non-volatile memory with multiple test clock speeds for multiple test modes

Abstract

Built-in self-test circuitry of a non-volatile memory device is presented for testing the data path between the input/output (IO) pads of a memory chip and the buffer memory used to store data to be written into or read out of a memory array. One set of tests on the data path can be high speed data path tests to determine whether the memory device can handle the transfer speed of user data transfer to and from the memory device. However, this requires data path testing based on a high speed test clock which may not be suitable for other test modes, such as setting trim values. To address this issue, the following presents testing techniques and circuitry for data path testing having multiple modes, in which the frequency of the test clock signal is divided by differing amounts depending on the test selected.