The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Sep. 03, 2023
Applicant:

Synopsys, Inc., Sunnyvale, CA (US);

Inventors:

Xun Liu, Cary, NC (US);

Jennifer Song Yon Pyon, Saratoga, CA (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
G06F 13/382 (2013.01); G06F 2213/40 (2013.01);
Abstract

A description of an interconnect channel within an interposer (such as a Universal Chiplet Interconnect Express™ (UCIe) channel) includes first bump locations for a first interface to the interconnect channel on a first die, second bump locations for a second interface to the interconnect channel on a second die, and nets connecting corresponding first and second bump locations for the two interfaces on the two dies. A processing device partitions the interconnect channel into subchannels. The subchannels include corresponding clusters of first and second bump locations connected by nets. The bounding boxes for the subchannels are non-overlapping. For each subchannel, the nets within the subchannel are routed.


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