The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Mar. 03, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Kwanyong Lim, San Diego, CA (US);

Hyunwoo Park, San Diego, CA (US);

Junjing Bao, San Diego, CA (US);

Haining Yang, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H10D 30/014 (2025.01); H10D 30/024 (2025.01); H10D 30/43 (2025.01); H10D 30/6211 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/151 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/038 (2025.01);
Abstract

Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a first gate structure disposed on a substrate and having a first channel length; a second gate structure disposed on the substrate and having the first channel length, a first source/drain space between the first gate structure and the second gate structure having a first distance; a third gate structure disposed on the substrate and having a second channel length; and a fourth gate structure disposed on the substrate and having the second channel length, a second source/drain space between the third gate structure and the fourth gate structure having a second distance. In an aspect, the second distance ranges from 0.75 times to 1.25 times the first distance.


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