The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Sep. 12, 2022
Applicant:

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;

Inventors:

Xuanxuan Chen, Quanzhou, CN;

Mingqin Shangguan, Quanzhou, CN;

Changfu Ye, Quanzhou, CN;

Tsuo-Wen Lu, Quanzhou, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
H10B 12/312 (2023.02); G11C 5/063 (2013.01); H10B 12/0335 (2023.02); H10B 12/488 (2023.02);
Abstract

A memory device and a manufacturing method thereof are disclosed in the present invention. The memory device includes a substrate, trenches, an oxide semiconductor layer, a gate dielectric layer, and word line structures. The substrate includes active regions and an isolation structure located between the active regions. The active regions contain silicon. The trenches are disposed in the active regions and the isolation structure. The oxide semiconductor layer is disposed in each trench. The gate dielectric layer is disposed on the oxide semiconductor layer and located in each trench. The word line structures are disposed on the gate dielectric layer and located in the trenches, respectively. At least a portion of the gate dielectric layer is disposed between the oxide semiconductor layer and each word line structure.


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