The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Sep. 03, 2021
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Ming Cheng, Hefei, CN;

Xing Jin, Hefei, CN;

Ran Li, Hefei, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/10 (2006.01); G11C 5/06 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 23/10 (2013.01); H10B 12/0335 (2023.02); H10B 12/315 (2023.02); H10B 12/482 (2023.02); G11C 5/063 (2013.01);
Abstract

A method for manufacturing a semiconductor structure includes: providing a substrate and a bit line structure located on the substrate, the bit line structure including a top dielectric layer and capacitive contact holes being provided on two opposite sides of the bit line structure; forming a first spacer covering a sidewall of the top dielectric layer between the bit line structure and the capacitive contact hole and a second spacer covering a sidewall of the first spacer, a top surface of the second spacer being higher than that of the first spacer; removing at least part of the top dielectric layer to form a first void; forming a first sealing film by a deposition process; and removing a part of the first sealing film which is higher than the top surface of the second spacer, the remaining first sealing film is a first sealing layer.


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