In-place refresh techniques for non-volatile memory devices

Abstract

The memory device includes a memory block that includes an array of memory cells that are arranged in a plurality of word lines. The memory device also includes circuitry for programming the memory cells of the memory block. The circuitry is configured to program the memory cells of the memory block to a single bit per memory cell storage format that includes a first data state and a second data state that is at a higher threshold voltage range than the first data state. In response to the memory cells experiencing data retention stress that causes the memory cells in the second data state to fall, the circuitry is configured to perform an in-place programming operation on a selected word line of the plurality of word lines. The in-place programming operation includes the circuitry programming the memory cells in the second data state to higher threshold voltages.