The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Mar. 24, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jonathan Y. Wang, Folsom, CA (US);

Yasir Mohsin Husain, Folsom, CA (US);

Ashraf B. Islam, El Dorado Hills, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
G11C 13/0038 (2013.01); G11C 13/0004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); H10B 63/84 (2023.02); G11C 2213/71 (2013.01); H10N 70/826 (2023.02); H10N 70/882 (2023.02);
Abstract

Techniques for current biasing for memory cells are disclosed. In the illustrative embodiment, a source follower sets a voltage on a bitline of a memory cell. The current through the source follower is limited by a current mirror in series with the source follower. When additional current is required that the source follower cannot supply, a feedback transistor is activated to provide additional current. Additionally, in some embodiments, the current through the feedback transistor is copied to a current mirror, and the copied current is used to sense the state of the memory cell.


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