The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Jan. 17, 2024
Applicant:

Synopsys, Inc., Sunnyvale, CA (US);

Inventors:

Harold Pilo, Underhill, VT (US);

Anurag Garg, Cupertino, CA (US);

Michael Lee, South Burlington, VT (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01);
Abstract

A method and circuit are provided for maintaining an operating voltage on a selected column with a plurality of bitcells in a memory when writing to the selected column. The method includes during an active write operation to the selected column, implementing an NMOS transistor NC to allow a bitcell-supply self-discharge (BSSD) to occur on the selected column, wherein the BSSD occurs by connecting a first drain voltage to an operating voltage connection of the selected column via the NMOS transistor NC to allow discharge of the operating voltage connection while limiting over-discharge of the selected column. The method further includes a PMOS select transistor PS to connect a second drain voltage to the operating voltage connection of the unselected column.


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