The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Jun. 26, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventor:

Jhon Jhy Liaw, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/412 (2006.01); H10B 10/00 (2023.01); H10D 30/62 (2025.01); H10D 84/83 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
G11C 11/412 (2013.01); H10B 10/12 (2023.02); H10D 30/62 (2025.01); H10D 84/834 (2025.01); H10D 84/853 (2025.01); H10D 30/6219 (2025.01);
Abstract

Static Random Access Memory (SRAM) cells and memory structures are provided. An SRAM cell according to the present disclosure includes a first pull-up gate-all-around (GAA) transistor and a first pull-down GAA transistor coupled to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled to form a second inverter, a first pass-gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass-gate GAA transistor coupled to an output of the second inverter and an input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.


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