The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

May. 30, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yen Lin Chung, Hsinchu, TW;

Kao-Cheng Lin, Hsinchu, TW;

Wei Min Chan, Hsinchu, TW;

Yen-Huei Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G06F 30/392 (2020.01); G11C 11/419 (2006.01); H10B 10/00 (2023.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); G06F 30/392 (2020.01); G11C 11/419 (2013.01); H10B 10/12 (2023.02); H10B 10/18 (2023.02); H10D 89/10 (2025.01);
Abstract

A memory macro includes an input/output (I/O) circuit positioned in a semiconductor wafer, a column of memory cells including first and second subsets of contiguous memory cells extending away from the I/O circuit in the semiconductor wafer, wherein the first subset is positioned between the I/O circuit and the second subset, a first bit line coupled to the I/O circuit and extending on one of a frontside or a backside of the semiconductor wafer along the first subset and terminating at the second subset, and a second bit line coupled to the I/O circuit and extending on the other of the frontside or the backside along the first and second subsets. Each memory cell of the first subset is electrically connected to the first bit line, and each memory cell of the second subset is electrically connected to the second bit line.


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