The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Nov. 24, 2023
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Tejas Nagendra Babu Nama, Palo Alto, CA (US);

Ruddhi Chaphekar, Palo Alto, CA (US);

Ram Sivaramakrishnan, San Jose, CA (US);

Raghu Prabhakar, San Jose, CA (US);

Sumti Jairath, Palo Alto, CA (US);

Junjue Wang, Newark, CA (US);

Kaizhao Liang, Palo Alto, CA (US);

Adi Fuchs, Palo Alto, CA (US);

Matheen Musaddiq, Austin, TX (US);

Arvind Krishna Sujeeth, Palo Alto, CA (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/78 (2006.01); G06F 16/901 (2019.01); G06F 17/16 (2006.01);
U.S. Cl.
CPC ...
G06F 15/7885 (2013.01); G06F 15/7839 (2013.01); G06F 16/9024 (2019.01); G06F 17/16 (2013.01);
Abstract

Disclosed is a method that includes sectioning a graph into a sequence of sections, the sequence of sections including at least a first section followed by a second section. The first section is configured to generate a first output in a first target tiling configuration in response to processing a first input in a first input tiling configuration. The graph is configured to reconfigure the first output in the first target tiling configuration to a second input in a second input tiling configuration. The second section is configured to generate a second output in a second target tiling configuration in response to processing the second input in the second input tiling configuration.


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