The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2025
Filed:
Dec. 04, 2023
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Aswin Thiruvengadam, Folsom, CA (US);
Daniel L. Lowrance, El Dorado Hills, CA (US);
Peter Feeley, Boise, ID (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/406 (2006.01); G06F 12/02 (2006.01); G06F 13/16 (2006.01); G06F 16/18 (2019.01); G11C 7/20 (2006.01); G11C 16/20 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01); G11C 29/02 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0292 (2013.01); G06F 12/0246 (2013.01); G06F 13/1694 (2013.01); G06F 16/1847 (2019.01); G11C 7/20 (2013.01); G11C 11/40607 (2013.01); G11C 16/20 (2013.01); G11C 16/32 (2013.01); G11C 16/3459 (2013.01); G11C 29/028 (2013.01); G06F 2212/7208 (2013.01); G06F 2212/7209 (2013.01); G11C 2029/4402 (2013.01); G11C 2211/5641 (2013.01);
Abstract
The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.