The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Mar. 27, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

John D. Leidel, McKinney, TX (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G11C 7/10 (2006.01); G11C 21/00 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0607 (2013.01); G06F 3/0659 (2013.01); G06F 3/0685 (2013.01); G06F 13/1621 (2013.01); G06F 13/1657 (2013.01); G06F 13/1673 (2013.01); G06F 13/1684 (2013.01); G06F 13/40 (2013.01); G06F 13/4022 (2013.01); G06F 13/4234 (2013.01); G11C 7/1075 (2013.01); G11C 21/00 (2013.01); G06F 2212/205 (2013.01);
Abstract

An interconnect system includes host devices, one or more memory devices, and a routing system to connect the host devices and the one or more memory devices. Respective ones of the host devices include an interface to communicate packet requests over respective packetized links. Respective ones of the one or more memory devices include an interface to receive and respond to the packet requests over the respective packetized links. The routing system includes devices interconnected in a routing topology. Respective ones of the devices include a switch and interfaces. The routing system is to route the packet requests and responses between the host devices and respective memory device destinations over the respective packetized links.


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