The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Dec. 01, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sergio Carlo Rodriguez, Hillsboro, OR (US);

Cary D Renzema, North Plains, OR (US);

Amit K. Jain, Sherwood, OR (US);

Po-Cheng Chen, Tigard, OR (US);

Fabrice Paillet, Portland, OR (US);

Anand Ramasundar, Portland, OR (US);

James Keith Hodgson, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/577 (2006.01); G05F 1/10 (2006.01);
U.S. Cl.
CPC ...
G05F 1/577 (2013.01); G05F 1/10 (2013.01);
Abstract

Embodiments herein relate to a feedback loop in a digital voltage regulator for controlling an output voltage. To avoid instability at light current loads, a gain of the loop is reduced as a power gate code indicates a reduced number of branches in set of current sources are enabled. In an example implementation, the code is classified into one range of a number of ranges, and the gain is set based on the one range. The gain can decrease each time the code enters a lower range, as indicated by the code crossing a threshold or predetermined value. For example, the gain can decrease by half each time the code enters a lower range.


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