The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Dec. 05, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Kisik Choi, Watervliet, NY (US);

Reinaldo Vega, Mahopac, NY (US);

Albert M. Chu, Nashua, NH (US);

Nicholas Anthony Lanzillo, Wynantskill, NY (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5286 (2013.01); H10D 30/6729 (2025.01); H10D 62/121 (2025.01); H10D 84/0149 (2025.01); H10D 84/83 (2025.01);
Abstract

One or more systems, devices, and/or methods of fabrication provided herein relate to reduced parasitic capacitance of power via bars. According to one embodiment, a semiconductor device can comprise a field-effect transistor (FET), and a power via bar coupled to a backside power rail, wherein the power via bar has greater height adjacent to a source and drain region of the field-effect transistor (FET) relative to a gate of the FET to mitigates parasitic capacitance within the device.


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