The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Jul. 17, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Osamu Nagashima, Kanagawa, JP;

Yoshinori Matsui, Kanagawa, JP;

Keun Soo Song, Boise, ID (US);

Hiroki Takahashi, Tokyo, JP;

Shunichi Saito, Kanagawa, JP;

Assignee:

MICRON TECHNOLOGY, INC., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); H03K 5/135 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 11/4087 (2013.01); H03K 5/135 (2013.01); H03K 2005/00078 (2013.01);
Abstract

A clock generator circuit may generate internal data clock signals, such as quadrature phase clock signals, based at least in part, on one clock signal responsive, at least in part, to another clock signal. The internal data clock signals may be generated from a system clock signal responsive to a data clock signal. The internal data clock signal may be generated by sampling the system clock signal. The sampling may be performed responsive to the data clock signal. A latch may latch a state of the system clock signal responsive to the data clock signal. The latch may output the internal data clock signal.


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